本文選題：數(shù)據(jù)采集 + 網(wǎng)絡(luò)協(xié)議��； 參考：《西安電子科技大學(xué)》2014年碩士論文

【摘要】：計(jì)算機(jī)和通信技術(shù)的迅猛發(fā)展,刺激著各個(gè)領(lǐng)域的進(jìn)步,特別是航空領(lǐng)域。少量的信息采集、記錄和顯示已經(jīng)無(wú)法滿足機(jī)載數(shù)據(jù)采集系統(tǒng)的需求,正往大量實(shí)時(shí)信號(hào)的記錄、處理、存儲(chǔ)和傳輸方向發(fā)展。在機(jī)載采集系統(tǒng)上安裝著大量的傳感器,這些傳感器能采集飛機(jī)飛行過(guò)程的環(huán)境信息,包括飛行高度、氣流壓力、溫度、風(fēng)向等。這些飛行環(huán)境經(jīng)過(guò)傳感器輸出為數(shù)字電平,電平經(jīng)過(guò)采樣、量化、編碼等步驟,以碼元的形式通過(guò)以太網(wǎng)實(shí)時(shí)傳輸送入計(jì)算機(jī)進(jìn)行處理、分析、存儲(chǔ)和顯示。作為數(shù)據(jù)采集系統(tǒng)的核心,微處理器一般都提供以太網(wǎng)接口,當(dāng)大量采集數(shù)據(jù)到來(lái)時(shí),其處理任務(wù)和網(wǎng)絡(luò)傳輸之間的矛盾就越發(fā)突出。在本文,大量模擬信號(hào)的實(shí)時(shí)傳輸,需要處理器的不斷運(yùn)轉(zhuǎn),考慮到減少處理器的運(yùn)算壓力、對(duì)采集系統(tǒng)FPGA資源的合理使用和飛行環(huán)境對(duì)機(jī)載設(shè)備體積、功耗等方面提出的嚴(yán)格要求,以嵌入式以太網(wǎng)為基礎(chǔ),提出了基于FPGA的嵌入式以太網(wǎng)接口設(shè)計(jì)的方案。論文主要工作如下:1、本文基于FPGA的高性價(jià)比、應(yīng)用廣泛和可靈活編程的特點(diǎn),采用了軟硬件協(xié)同編程的方式完成設(shè)計(jì)。以Altera公司的CycloneIII系列為平臺(tái),搭建了以軟核處理器NiosII為核心包含多種外設(shè)的可編程片上系統(tǒng)(SoPC),其中最主要的外設(shè)是以太網(wǎng)的核心媒體接入控制器(MAC)。利用Altera公司的三速以太網(wǎng)(TSE)IP核,在FPGA內(nèi)實(shí)現(xiàn)以太網(wǎng)MAC協(xié)議,并提供了標(biāo)準(zhǔn)介質(zhì)獨(dú)立接口(MII)。該接口與擴(kuò)展的物理(PHY)芯片相連,完成網(wǎng)絡(luò)傳輸?shù)牡讓釉O(shè)計(jì)。PHY芯片DP83640,該芯片體積小、功耗低但功能強(qiáng)大,并提供了精簡(jiǎn)介質(zhì)獨(dú)立接口(RMII)。2、網(wǎng)絡(luò)接口設(shè)計(jì)位于網(wǎng)絡(luò)通信的最底層,為了實(shí)現(xiàn)完整的以太網(wǎng)通信,在軟件設(shè)計(jì)中,完成了三速以太網(wǎng)MAC和DP83640的驅(qū)動(dòng)設(shè)計(jì),并系統(tǒng)的移植了輕量級(jí)TCP/IP協(xié)議�！狶wip,為了減少內(nèi)存占用,本文是移植無(wú)操作系統(tǒng)Lwip,并根據(jù)協(xié)議棧實(shí)現(xiàn)了UDP的數(shù)據(jù)傳輸,并提供了上層應(yīng)用程序調(diào)用的接口(API)�；贔PGA的嵌入式以太網(wǎng)接口設(shè)計(jì)從機(jī)載數(shù)據(jù)采集環(huán)境需求出發(fā),充分利用了FPGA的高速、實(shí)時(shí)、可編程特性,經(jīng)過(guò)測(cè)試,網(wǎng)絡(luò)傳輸性能達(dá)到了系統(tǒng)指標(biāo)要求。
[Abstract]:The rapid development of computer and communication technology stimulates the progress in various fields, especially in aviation. A small amount of information acquisition, recording and display can no longer meet the requirements of airborne data acquisition system, and is developing towards the direction of recording, processing, storage and transmission of a large number of real-time signals. A large number of sensors are installed on the airborne acquisition system, which can collect the environmental information of the flight process of the aircraft, including flight altitude, air pressure, temperature, wind direction and so on. These flying environments are output to digital level by sensor, the level is sampled, quantized, coded and sent to computer to process, analyze, store and display through Ethernet real-time transmission in the form of symbol. As the core of data acquisition system, microprocessor generally provides Ethernet interface. When a large amount of data is collected, the contradiction between processing task and network transmission becomes more and more prominent. In this paper, the real-time transmission of a large number of analog signals requires the continuous operation of the processor. In order to reduce the computational pressure of the processor, the reasonable use of the FPGA resources of the acquisition system and the volume of the airborne equipment in the flight environment are considered. Based on the strict requirement of power consumption and embedded Ethernet, the design of embedded Ethernet interface based on FPGA is proposed. The main work of this paper is as follows: 1. Based on the high performance-to-price ratio of FPGA, this paper has the characteristics of wide application and flexible programming, and adopts the method of hardware and software co-programming to complete the design. Based on the CycloneIII series of Altera Company, a programmable on-chip system with a soft core processor NiosII as the core is built, in which the main peripheral device is the Ethernet core media access controller (MAC). Using Altera's three-speed Ethernet TSE IP core, the Ethernet MAC protocol is implemented in FPGA, and a standard medium independent interface is provided. The interface is connected with the extended PHY chip, and the bottom design of the network transmission is DP83640. The chip is small, low power and powerful, and provides the RMII / 2 independent interface. The network interface design lies at the bottom of the network communication. In order to realize the complete Ethernet communication, the driver design of three-speed Ethernet MAC and DP83640 is completed in the software design, and the lightweight TCP/IP protocol stack is transplanted into the system. In this paper, we transplant the Lwip without operating system, realize the data transmission of UDP according to the protocol stack, and provide the interface of calling by the upper application program. The design of embedded Ethernet interface based on FPGA is based on the requirement of airborne data acquisition environment, and makes full use of the high-speed, real-time and programmable characteristics of FPGA. After testing, the network transmission performance meets the requirements of the system.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TP393.11

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相關(guān)碩士學(xué)位論文 前2條

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本文編號(hào)：1901782