本文選題：嵌入式以太網(wǎng) + 數(shù)據(jù)傳輸��； 參考：《液晶與顯示》2017年08期

【摘要】：在含有FPGA的數(shù)字信號處理電路和控制電路中,為了實(shí)現(xiàn)將原始AD采樣數(shù)據(jù)或中間處理結(jié)果數(shù)據(jù)的導(dǎo)出,供后續(xù)分析處理使用,從數(shù)據(jù)傳輸?shù)姆�(wěn)定性、系統(tǒng)實(shí)現(xiàn)的簡易性、價(jià)格低廉等角度出發(fā),研究設(shè)計(jì)了基于FPGA TSE IP核的嵌入式百兆以太網(wǎng)數(shù)據(jù)傳輸系統(tǒng)。首先,詳細(xì)分析了以NiosII CPU軟核處理器為核心的以太網(wǎng)數(shù)傳系統(tǒng)的SOPC各模塊的硬件設(shè)計(jì),主要包括以TES IP核為主的以太網(wǎng)MAC,采用乒乓緩存方式保證數(shù)據(jù)的連續(xù)不間斷傳輸,以及通過接收客戶端指令來控制數(shù)傳的開始和暫停;然后,利用MicroC/OS-II嵌入式實(shí)時(shí)操作系統(tǒng)的多任務(wù)方式,基于Niche stack TCP/IP協(xié)議棧,完成了系統(tǒng)的軟件設(shè)計(jì),并給出了軟件程序流程;最后,通過傳輸并接收特定的數(shù)據(jù),驗(yàn)證了系統(tǒng)數(shù)據(jù)傳輸?shù)乃俾屎蜏?zhǔn)確性。結(jié)果表明在傳輸速率達(dá)到51 Mbps時(shí),系統(tǒng)穩(wěn)定可靠。
[Abstract]:In the digital signal processing circuit and control circuit containing FPGA, in order to export the original AD sampling data or intermediate processing result data for subsequent analysis and processing, the stability of data transmission and the simplicity of system realization are obtained. From the point of view of low price, the embedded data transmission system based on FPGA TSE IP core is studied and designed. Firstly, the hardware design of SOPC module of Ethernet data transmission system based on NiosII CPU soft core processor is analyzed in detail, which mainly includes Ethernet Mac, which is based on TES IP core, and uses ping-pong buffer to ensure the continuous transmission of data. Then, using the multi-task mode of MicroC/OS-II embedded real-time operating system, based on the Niche stack TCP/IP protocol stack, the software design of the system is completed, and the software program flow is given. Finally, the rate and accuracy of system data transmission are verified by transmitting and receiving specific data. The results show that the system is stable and reliable when the transmission rate reaches 51 Mbps.
【作者單位】： 中國科學(xué)院長春光學(xué)精密機(jī)械與物理研究所;電子科技大學(xué)通信與信息工程學(xué)院;
【分類號】：TN791;TP393.11
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本文編號：1879977